Comparison between optimization techniques for Y-junction devices in SOI substrates

Abstract

We report the comparison between three optimization methods used for the design of Y-junction in terms of convergence velocity, maximum transmitted power and fabrication feasibility. The optimization techniques include Particle Swarm Optimization, Shrinking Box algorithm and Steepest Ascent algorithm. we demonstrate transmittance values of 49% in the case of the splitter and near 96% in the case of the combiner with areas on chip down to 2.05 μm2. The practical application of this work is to design compact, low-loss and wavelength independent splitters and combiners for sub-micron silicon-on-insulator(SOI) photonic integrated circuits, compatible with typical commercial standard microfabrication processes.